MAX5948BESA+T【PDF 10/18 页】IC CNTRLR HOT SWAP 8-SOIC

-48V Hot-Swap Controllers

with External R

SENSE

10 ______________________________________________________________________________________

If more than 3祍 (typ) deglitch time (t

PHLSENSE

) is

needed to prevent spurious shutdown due to load cur-

rent spikes or noise, a simple lowpass filter can be

used between the SENSE and V

EE

pins as shown in

Figure 9. Resistor R7 and capacitor C3 slow down the

response of the circuit breaker to filter momentary

glitches in the SENSE voltage. The additional delay

time can be estimated with the following equation:

where I

f

is the current in fault condition, I

I

is the initial

current before the fault, and I

CB

is the circuit-breaker

trip current (I

CB

= V

CB

/R1). Alternatively, the corre-

sponding voltages across the sense resistor (V

f

, V

I

, and

V

CB

) may be used in the equation as shown. The

SENSE pin of the MAX5948A/MAX5948B sources very

little current (0.02礎 typ), so the addition of resistor R7

will introduce very little error in the circuit-breaker trip

voltage. For example, a 10k& resistor for R7 will only

cause a 200礦 offset.

Example: A system has a 1A nominal load current and

a 20m& sense resistor. The circuit-breaker delay needs

to be increased to 50祍 in response to a load current

step to 5A. The circuit-breaker trip current is

50mV/20m& = 2.5A. Solving for R7 x C3 in the equation

above yields a desired time constant of 100祍. This can

be achieved with R7 = 100& and C3 = 1礔.

t

R C In

V V

R C In

I I

cbdly

f

I

f

CB

f I

f CB

= ?nbsp ?/DIV>

?/DIV>

= ?nbsp ?/DIV>

?/DIV>

7 3

GATE - V

EE

5V/div

V

EE

50V/div

INRUSH

CURRENT

2A/div

4ms/div

CONTACT

BOUNCE

Figure 8. Startup Into a Short Circuit

V

EE

SENSE

GATE

DRAIN

V

DD

OV

UV

PWRGD

MAX5948A

-48V RTN

-48V

R4

562k&

1%

R5

9.09k&

1%

R6

10k&

1%

R1

0.02&

5%

R3

18k&

5%

R2

10&

5%

C1

150nF

25V

Q1

IRF530

C2

3.3nF

100V

C4

100礔

100V

*

-48V RTN

(SHORT PIN)

*DIODES INC. SMAT70A.

C3

R7

Figure 9. Extending the Short-Circuit Protection Delay

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